Saturday, June 29, 2013

Embedded Systems Final Project: Programmable IIR/FIR Digital Filter

For my final project in Embedded Systems I designed a reprogrammable  infinite impulse response (IIR) / finite impulse response (FIR) filter.

This project used a ATmega88pa (a little bit overkill, but it was readily available to us) with a 8 MHz clock, and an 8-bit DAC (AD557JN).  An anti-aliasing lowpass filter before the microcontroller's ADC and an analog reconstruction lowpass filter after the DAC to remove the "stair step" output of the DAC were planned to be implemented.

The program was designed to follow the flow graph shown below. The signal coming in is added to scaled versions of values stored in a circular buffer. This feedback from the buffer creates the IIR part of filter. This value is then stored as the head of the circular buffer. Scaled versions of all the saved values in the buffer are then added together and sent to the DAC as output.

Different filters could be programmed into the filter by simply changing the scaling coefficients stored in the program. These coefficients were determined using MATLAB. We were able to implement the all main types filters (highpass, lowpass, bandpass, notch) with this design.

To ensure that the program would be fast enough to process meaningful signals, the entire project was programmed in assembly. Counting the cycles of the main loop of the program the minimum clock cycles needed for a first order filter was 108 each cycle. With an 8 MHz crystal the theoretical fastest sampling rate was about 37 kHz. That's really good considering that I was hoping to filter signals in the 60-120 Hz range and you can accurately reproduce audio with a sampling rate greater than about 40 kHz.

Unfortunately, I left the anti-aliasing and reconstruction filter design to my partner for this project. They never actually worked. However, using a function generator to create a fairly clean signal we were able to not worry about aliasing for testing purposes, and we were able to use the averaging function on the oscilloscope as an FIR low-pass reconstruction filter. The following oscilloscope screen captures are of a 60 Hz notch filter with a sampling rate of  400 samples per second.

The top plot is the input composed of signals at 42 Hz and 60Hz.
The bottom plot is the 42 Hz output from the 60 Hz notch filter.

The top plot is the input to the filter composed of 130 Hz and 60Hz Signals.
The bottom plot is the output of the 60Hz notch filter.

With a 60 Hz bandpass filter, we measured a bandwidth of about 3 Hz. This corresponds with a Q of about 20 which is really pretty good. We were running short on time and did not get around to monitoring the systems power consumption.

Overall, the programming and idea of the filter worked out great. Here is a picture of the system. It's not pretty. The DAC was soldered to the underside of the board (where all the yellow wires are running to). You will notice we didn't remove the unused USART section from our development board. Ideally the system would be a subsystem of a larger system, and won't need it's own power supply either.

Finished Prototype

The main change I would make to this project would be using 16-bit or 32-bit values rather than 8-bit values throughout the entire project. The inaccuracy in the values made it hard to design for a specific frequency and bandwidth at higher sampling rates. A wider range of frequencies the system can process results in each bit representing an wider range of frequencies. Also it would have been nice to have had the anti-aliasing and reconstruction filters working, and measured the power consumption of the system.